1. Field of the Invention
The present disclosure relates to a semiconductor memory device and, more particularly, to a nonvolatile memory device including a page buffer.
A claim for priority is made to Korean Patent Application No. 2005-107755 filed on Nov. 10, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Generally, semiconductor memory devices may be categorized as volatile memory devices or nonvolatile memory devices. The volatile memory devices may be classified into dynamic random access memories (DRAMs) and static random access memories (SRAMs). The volatile semiconductor devices lose their data when their power supplies are interrupted, while nonvolatile memory devices retain their stored data even when their power supplies are interrupted. Thus, the nonvolatile memories are widely used to store retention-required data that is unaffected by power supply interruption. Nonvolatile memory may include memories such as, for example, mask read-only memories (MROMs), programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), and electrically erasable programmable read-only memories (EEPROMs).
However, MROMs, PROMs, and EPROMs may have difficulty in rewriting stored data because read and write operations may not be freely conducted by users on these devices. On the other hand, EEPROMs are increasingly used in system programming that requires the continuous update of auxiliary memory devices. In particular, (flash) EEPROMs may be advantageous in their use as mass storage devices because their integration density may be higher than conventional EEPROMs. Among these flash EEPROMs, NAND-type flash EEPROM (hereinafter referred to as “NAND flash memory devices”) may have much higher integration density than other flash EEPROMs.
The configuration of a conventional NAND flash memory device 10 is illustrated in FIG. 1. The NAND flash memory device 10 includes a memory cell array 11, a row decoder 12, and a page buffer circuit 14. The memory cell array 11 is a data storage unit which includes memory cells arranged at intersections of rows (i.e., wordlines) and columns (i.e., bitlines). A NAND string includes memory cells each storing 1-bit data or multi-bit data. The rows of the memory cell array 11 may be driven by the row decoder circuit 12, and the columns thereof may be driven by the page buffer circuit 14.
The page buffer circuit 14 programs/reads 1-bit data or multi-bit data (e.g., 2-bit data) to/from each memory cell. Because flash memory devices are now being required to support a variety of operations, the page buffer circuit 14 may support additional operations such as, for example, a cache program operation, and a page copyback operation. The cache program operation includes an operation wherein while data of one page is programmed, data to be stored for the next page is loaded on the page buffer circuit 14. The page copyback operation includes an operation wherein data stored in any page is moved to another page through the page buffer circuit 14, without being outputted to a circuit external to the page buffer circuit 14.
A plurality of page buffers may be provided in the page buffer circuit 14. Furthermore, one or more latches may be provided in each of the page buffers. Each of the page buffers stores cell data sensed at a sense node in a latch during a normal read operation or a page copyback operation. In addition, each page buffer also stores data to be programmed in a latch during a normal program operation or a cache program operation. The time at which data may be stored in a latch may be controlled by a control logic block (not shown) provided outside the NAND flash memory device 10. In addition, each latch may store data using a power supply voltage as a source. In an event that all latches constructed in the page buffer circuit 14 are activated, current flowing along a data path may increase rapidly for a short period of time thereby causing a drop in power supply voltage.
In order to prevent a drop of a power supply voltage, the page buffers of the page buffer circuit 14 may be split into several groups (e.g., eight groups) of page buffers. Latches constructed in the groups of the page buffer group may be sequentially activated for very short intervals during an activation period. However, although the groups of the latches are sequentially activated, a power supply voltage may encounter a voltage drop caused by the load capacitance element in a page buffer. For example, when groups of latches are activated, a voltage applied to a latch node may drop below a trip point due to charge sharing between internal nodes connected to a latch. As a result, a data value stored in a latch may be inverted. This variation of data value stored in a latch may be called “latch noise”.
The present disclosure is directed to overcoming one or more of the problems associated with the conventional flash memory devices.